At modern age, the semiconductor device becomes smaller and smaller because of the improvement of the manufacturing technology from micron, sub-micron to deep sub-micron. According to the requirement of the accuracy, the backend planarization process gets more important. The so-called planarization process is a process for planarizing the uneven surface of a dielectric layer to obtain a smooth surface. After the planarization process, the dielectric layer has a more smooth surface. Thus, the subsequent processes for forming other layers over the dielectric layer become easier and the patterns transferring to the layers are more reliable. The most often used backend planarization processes are spin-on-glass (SOG) process and chemical mechanical polishing (CMP) process. These processes can provide a locally or globally planarized surface and are suitable for recent semiconductor manufacturing process. The spin-on-glass process can fill gap well so that it is adopted widely to manufacture semiconductor devices. The spin-on-glass processes are further classified into two types, with and without etch-back step. The former can prevent the spin-on-glass layer from outgassing when curing the spin-on-glass layer. However, it is still disadvantageous to adopt such backend planarization process. If the area of the metal under the dielectric layer is larger than 3.0 .mu.m.times.3.0 .mu.m, there is always residue spin-on-glass on the metal line. The residue will seriously affect the quality of the semiconductor device.
FIG. 1 shows the conventional method for manufacturing a semiconductor structure having a via hole. Please refer to FIG. 1(A). At first, a metal layer 11 is deposited on a half-finished semiconductor device 10. The half-finished semiconductor device 10 may be a complementary metal-oxide semiconductor (CMOS) formed by a conventional process. Secondly, as shown in FIG. 1(B), a typical etching step is executed. The etching step includes a) depositing a photoresist layer 12 on the metal layer 11, b) transferring pattern to the photoresist layer 12 by photolithography, c) etching the metal layer 11 to form a relatively broad metal line 111 and a relatively narrow metal line 112, and d) stripping the photoresist layer 12.
Thirdly, referring to FIG. 1(C), a dielectric layer 13 is deposited over the metal lines 111 and 112. The dielectric layer 13 is usually a silicon dioxide (SiO.sub.2) layer with a thickness of 2000 .ANG.. Plasma enhanced chemical vapor deposition (PECVD) is the most often used method to deposit the dielectric layer 13 because of its relative low reaction temperature, good step coverage ability, and low residuary stress of the deposited layer. There is a gap 14 formed between the metal lines 111 and 112. Then, the spin-on-glass process is used for filling the gap 14. The thickness of the spin-on-glass layer 15 is about 5000 .ANG.. However, there are still protrusions 16 right over the metal lines 111 and 112. Please refer to FIG. 1(D). After curing the spin-on-glass layer 15, reflow occurs so that the spin-on-glass layer 15 becomes planarized, but not fully even. The protrusion 161 right over the broad metal line 111 is thicker than the protrusion 162 right over the narrow metal line 112.
Please refer to FIG. 1(E). The etch-back step is executed to remove the upper portion of the spin-on-glass layer 15. The spin-on-glass layer 15 right over the metal lines 111 and 112 must be fully removed. However, it is difficult to remove completely when the area of the metal line is larger than 3.0 .mu.m.times.3.0 .mu.m. Because the protrusion 161 right over the broad metal line 111 is thicker than the protrusion 162 right over the narrow metal line 112, there must be a residue 163 remained over the broad metal line 111 after the etch-back step. Then, referring to FIG. 1(F), the plasma enhanced chemical vapor deposition is executed again to deposit another silicon dioxide layer 17 with a thickness of 5000 .ANG.over the spin-on-glass layer 15. The spin-on-glass layer 15 and two silicon oxide layers 13 and 17 constitute the so-called sandwich type structure. The planarization process is completed and a locally planarized surface is obtained.
Multilevel metallization schemes play an important role in very-large-scale integration (VLSI) technology because they provide additional surface area on which interconnections can be made. In order to perform the multilevel metallization, a via plug is necessary for connecting different metal lines. Please refer to FIG. 1(G). The via holes 181 and 182 are formed on the metal lines 111 and 112 for positioning the via plugs. The problem is that the residue 163 is exposed to the environment. The residue 163 which has a silicon dioxide-like property will absorb moisture so that the residue 163 will expand and deform. If the exposure of the residue 163 takes too much time, e.g. more than 6 hours, the reliability and quality of the device is seriously affected. The competitive ability of such devices must be reduced. Increasing the etch-back time has been proposed to fully remove the residue. However, the other portion of the spin-on-glass layer is thinned by this way and it can not provide good insulation any more. Another problem is that the residue 163 increases the depth of the via hole 181. The etching step can not be well controlled to completely remove the dielectric layer 13 in the via hole 181 because the thickness of residue 163 can not be easily controlled. There is residuary dielectric material 164 remained in the via hole 181. Therefore, the electrical connection between two metal layers is seriously affected. It is really disadvantageous to the development of multilevel metallization. The performance of the subsequent planarization is also seriously affected.